ADMS 2020
Eleventh International Workshop on Accelerating Analytics and Data Management Systems Using Modern Processor and Storage Architectures

Monday, August 31, 2020
In conjunction with VLDB 2020
Online Presentations Only
Workshop Overview

The objective of this one-day workshop is to investigate opportunities in accelerating data management systems and analytics workloads (which include traditional OLTP, data warehousing/OLAP, ETL, Streaming/Real-time, Analytics (including Machine Learning), and HPC/Deep Learning) using processors (e.g., commodity and specialized Multi-core, GPUs, FPGAs, and ASICs/SOCs), high-speed networking, storage systems (e.g., Storage-class Memories like SSDs and Phase-change Memory), programming models like Spark, CUDA/OpenCL, and environments such as various Python-based data science infrastructures (e.g., Nvidia RAPIDS), on on-prem or cloud-based systems.

The current data management scenario is characterized by the following trends: traditional OLTP and OLAP/data warehousing systems are being used for increasing complex workloads (e.g., Petabyte of data, complex queries under real-time constraints, etc.); applications are becoming far more distributed, often consisting of different data processing components; non-traditional domains such as bio-informatics, social networking, mobile computing, sensor applications, gaming are generating growing quantities of data of different types; economical and energy constraints are leading to greater consolidation and virtualization of resources; and analyzing vast quantities of complex data is becoming more important than traditional transactional processing.

At the same time, there have been tremendous improvements in the CPU and memory technologies. Newer processors are more capable in the CPU and memory capabilities and are optimized for multiple application domains. Commodity systems are increasingly using multi-core processors with more than 20 cores per chip and enterprise-class systems are using processors with even more cores per chip, where each core can execute upto 4 simultaneous threads. Specialized multi-core processors such as the GPUs have brought the computational capabilities of supercomputers to cheaper commodity machines. On the storage front, non-volatile memories (NVMe) and solid state devices (SSDs) are becoming smaller in size, cheaper in price, and larger in capacity. Exotic technologies like DNA storage are on the near-term horizon and can be game-changers in the way data is stored and processed.

In spite of the trends, currently there is limited usage of these technologies in data management domain. Naive usage of multi-core processors or SSDs often leads to unbalanced system. It is therefore important to evaluate applications in a holistic manner to ensure effective utilization of CPU and memory resources. This workshop aims to understand impact of modern hardware technologies on accelerating core components of data management workloads. Specifically, the workshop hopes to explore the interplay between overall system design, core algorithms, query optimization strategies, programming approaches, performance modelling and evaluation, etc., from the perspective of data management applications.

Topics of Interest

The suggested topics of interest include, but are not restricted to:

  • Hardware and System Issues in Domain-specific Accelerators
  • New Programming Methodologies for Data Management Problems on Modern Hardware
  • Query Processing for Hybrid Architectures
  • Large-scale I/O-intensive (Big Data) Applications
  • Parallelizing/Accelerating Machine Learning/Deep Learning Workloads
  • Autonomic Tuning for Data Management Workloads on Hybrid Architectures
  • Algorithms for Accelerating Multi-modal Multi-tiered Systems
  • Energy Efficient Software-Hardware Co-design for Data Management Workloads
  • Parallelizing non-traditional (e.g., graph mining) workloads
  • Algorithms and Performance Models for modern Storage Sub-systems
  • Exploitation of specialized ASICs
  • Novel Applications of Low-Power Processors and FPGAs
  • Exploitation of Transactional Memory for Database Workloads
  • Exploitation of Active Technologies (e.g., Active Memory, Active Storage, and Networking)
  • New Benchmarking Methodologies for Accelerated Workloads
  • Applications of HPC Techniques for Data Management Workloads
  • Acceleration in the Cloud Environments
  • DNA-inspired storage and processing
  • Exploitation of Quantum Technologies

Keynote Presentations

We have two keynote speakers for the upcoming VLDB’20 workshop:

  • Prof. Sang Kyun Cha, Seoul National University, will present his perspectives on present and future of in-memory databases
  • Prof. Masanori Hashimoto, Osaka University, will talk about FPGA acceleration opportunities for machine learning workloads.

Workshop Program: Session 1
11 am EST, 3 pm UTC (Time Block 2)

Session Chair: Rajesh Bordawekar
Session Links: Zoom Link   Slack Link   Conference Program Link

Workshop Program: Session 2
5 pm EST, 9 pm UTC (Time Block 3)

Session Chair: Tirthankar Lahiri
Session Links: Zoom Link   Slack Link   Conference Program Link

  • (5-5.30 pm EST, 9-9.30 pm UTC) When Vectorwise Meets Hyper, Pipeline Breakers Become the Moderator, Balasubramanian Gurumurthy, Imad Hajjar, David Broneske, Thilo Pionteck and Gunter Saake (Links: Youtube video Bilibili video Paper PDF)
  • (5.30-6 pm EST, 9.30-10 pm UTC) Enabling NUMA-aware Main Memory Spatial Join Processing: An Experimental Study, Suprio Ray, Catherine Higgins, Vaishnavi Anupindi and Saransh Gautam (Links: Youtube video Bilibili video Paper PDF)
  • (6-6.30 pm EST, 10-10.30 pm UTC) Parallel Prefix Sum with SIMD, Wangda Zhang, Yanbin Wang and Kenneth Ross (Links: Youtube video Bilibili video Paper PDF)
  • (6.30-7 pm EST, 10.30-11 pm UTC)Efficient Usage of One-Sided RDMA for Linear Probing, Tinggang Wang, Shuo Yang, Hideaki Kimura, Garret Swart and Spyros Blanas (Links: Youtube video Bilibili video Paper PDF)
  • (7-8 pm EST, 11 pm-12 am UTC) Keynote Presentation (2): Ambient AI: Connecting Physical and Digital Worlds, Prof. Sang Cha, Seoul National University (Links: Keynote Presentation (PDF))


Workshop Co-Chairs

       For questions regarding the workshop please send email to

Program Committee

  • Anuva Kulkarni, CMU
  • Yulhwa Kim, POSTECH
  • Kise Kenji, Tokyo Institute of Technology
  • Toshiyuki Amagasa, University of Tsukuba
  • Nikolay Sakharnykh, Nvidia
  • Dominik Durner, TU Munich
  • Lisa Wu Wills, Duke University
  • Berni Schiefer, AWS
  • Periklis Chrysogelos, EPFL
  • Meena Arunachalam, Intel
  • Minsik Cho, IBM Systems
  • Pinar Tozün, IT University of Copenhagen
  • Lasse Thostrup, TU Darmstadt
  • Jianting Zhang, CUNY
  • Kazuaki Ishizaki, IBM Tokyo Research Laboratory
  • Hiroki Matsutani, Keio University
  • Wei Wei Gong, Oracle
  • Steffen Zeuch, DFKI, TU Berlin

Important Dates

  • Paper Submission: Monday, 29 June, 2020, 9 am EST
  • Notification of Acceptance: Friday, 17 July, 2020
  • Camera-ready Submission: Friday, 24 July, 2020
  • Workshop Date: Monday, 31 August, 2020

Submission Instructions

Submission Site 

All submissions will be handled electronically via EasyChair.

Formatting Guidelines 

We will use the same document templates as the VLDB20 conference. You can find them here.

It is the authors' responsibility to ensure that their submissions adhere strictly to the VLDB format detailed here. In particular, it is not allowed to modify the format with the objective of squeezing in more material. Submissions that do not comply with the formatting detailed here will be rejected without review. 

As per the VLDB submission guidelines, the paper length for a full paper is limited to 12 pages, excluding bibliography. However, shorter papers (at least 6 pages of content) are encouraged as well.