ADMS 2017
Eighth International Workshop on Accelerating Analytics and Data Management Systems Using Modern Processor and Storage Architectures

Friday, September 1, 2017
In conjunction with VLDB 2017
Auditorium 606, TU Munich, Munich, Germany
Workshop Overview

The objective of this one-day workshop is to investigate opportunities in accelerating data management systems and workloads (which include traditional OLTP, data warehousing/OLAP, ETL, Streaming/Real-time, Business Analytics, and XML/RDF Processing) using processors (e.g., commodity and specialized Multi-core, GPUs, FPGAs, and ASICs), storage systems (e.g., Storage-class Memories like SSDs and Phase-change Memory), and programming models like MapReduce, Spark, CUDA, OpenCL, and OpenACC.

The current data management scenario is characterized by the following trends: traditional OLTP and OLAP/data warehousing systems are being used for increasing complex workloads (e.g., Petabyte of data, complex queries under real-time constraints, etc.); applications are becoming far more distributed, often consisting of different data processing components; non-traditional domains such as bio-informatics, social networking, mobile computing, sensor applications, gaming are generating growing quantities of data of different types; economical and energy constraints are leading to greater consolidation and virtualization of resources; and analyzing vast quantities of complex data is becoming more important than traditional transactional processing.

At the same time, there have been tremendous improvements in the CPU and memory technologies. Newer processors are more capable in the CPU and memory capabilities and are optimized for multiple application domains. Commodity systems are increasingly using multi-core processors with more than 6 cores per chip and enterprise-class systems are using processors with 8 cores per chip, where each core can execute upto 4 simultaneous threads. Specialized multi-core processors such as the GPUs have brought the computational capabilities of supercomputers to cheaper commodity machines. On the storage front, FLASH-based solid state devices (SSDs) are becoming smaller in size, cheaper in price, and larger in capacity. Exotic technologies like Phase-change memory are on the near-term horizon and can be game-changers in the way data is stored and processed.

In spite of the trends, currently there is limited usage of these technologies in data management domain. Naive usage of multi-core processors or SSDs often leads to unbalanced system. It is therefore important to evaluate applications in a holistic manner to ensure effective utilization of CPU and memory resources. This workshop aims to understand impact of modern hardware technologies on accelerating core components of data management workloads. Specifically, the workshop hopes to explore the interplay between overall system design, core algorithms, query optimization strategies, programming approaches, performance modelling and evaluation, etc., from the perspective of data management applications.

Topics of Interest

The suggested topics of interest include, but are not restricted to:

  • Hardware and System Issues in Domain-specific Accelerators
  • New Programming Methodologies for Data Management Problems on Modern Hardware
  • Query Processing for Hybrid Architectures
  • Large-scale I/O-intensive (Big Data) Applications
  • Parallelizing/Accelerating Analytical (e.g., Data Mining) Workloads
  • Autonomic Tuning for Data Management Workloads on Hybrid Architectures
  • Algorithms for Accelerating Multi-modal Multi-tiered Systems
  • Energy Efficient Software-Hardware Co-design for Data Management Workloads
  • Parallelizing non-traditional (e.g., graph mining) workloads
  • Algorithms and Performance Models for modern Storage Sub-systems
  • Exploitation of specialized ASICs
  • Novel Applications of Low-Power Processors and FPGAs
  • Exploitation of Transactional Memory for Database Workloads
  • Exploitation of Active Technologies (e.g., Active Memory, Active Storage, and Networking)
  • New Benchmarking Methodologies for Storage-class Memories
  • Applications of HPC Techniques for Data Management Workloads
  • Acceleration in the Cloud Environments

Keynote Presentations

Every year, we choose a theme around which the keynote or panel sessions are organized. This year, the workshop theme is acceleration of machine learning and deep learning workloads.

Accelerating AI, John Ashley, Director, Global Professional Services, Nvidia

NVIDIA is a leader in the AI revolution, and in this talk we explore some of the reasons why. A quick review of trends in GPU computing leads into a review of key features of the CUDA software architecture, especially the use of PTX for forward compatibility, and relate them to our approach to silicon. We discuss innovation across recent chip generations – HBM2 memory, Chip on Wafer on Substrate, NVLink, and TensorCores -- and highlight some information about the latest NVIDIA chips and libraries for AI. A quick look ahead at new analytic initiatives like GPU Open Analytics highlights the convergence of HPC, AI, and Analytics.

Alice in Wonderland, the Red Queen’s race, and microprocessor design in a world of Deep Learning, Tim Mattson, Senior Principal Engineer, Intel

For better or worse, Machine Learning (ML), and Deep Learning (DL) in particular, are transforming the face of computing. Software Frameworks and domain specific languages have reduced the barrier of entry to ML/DL, so programmers across the spectrum of computing are deploying ML/DL solutions in new and creative ways. This presents a unique challenge to microprocessor designers. Software moves faster than hardware. How can processors adapt and keep up with this rapid pace of evolution? Perhaps our only hope is to focus on the fundamental primitives of ML/DL algorithms. While the ways these primitives are combined to create new ML/DL applications continues to change, the primitives themselves evolve slowly; hopefully at a pace hardware designers can keep up with. In this talk we will highlight the key primitives of ML/DL algorithms and explore how they are pushing the design of next generation microprocessors.

Anatomy of Cloud native Cognitive System, Aroop Pandya, Senior Technical Staff Member, IBM Watson

Recently, cognitive systems such as IBM Watson have made great strides in impacting many fields that are of fundamental relevance to society, from healthcare, to security and beyond. This has unleashed a torrent of innovation in cognitive systems that encompass a broad spectrum of computer science and engineering, from hardware infrastructure, to software stack, as­-a­-service platform layer, and finally data layer and cognitive applications. This talk will give an overview of the anatomy of a true cognitive system that lives and breathes in the cloud and will address key challenges that need to be addressed in the future.

Workshop Program

Session 1 (8.30 am - 10.00 am)

  • (8.35 am-9 am) The Five-minute Rule Thirty Years Later and its Impact on the Storage Hierarchy, Raja Appuswamy (EPFL), Renata Borovica-Gajic (Univ. of Melbourne), Goetz Graefe (Google) and Anastasia Ailamaki (EPFL) (Slides)

  • (9 am -10 am) "Accelerating AI", John Ashley, Director, Global Professional Services, Nvidia (Slides)

Coffee Break (10 am -10.30am)

Session 2 (10.30 am - 12.00 pm)

  • (10.30 am - 10.55 am) Exploring Query Compilation Strategies for JIT, Vectorization and SIMD, Tim Gubner and Peter Boncz (CWI) (Slides)

  • (10.55 am - 11.20 am) A Cost Model for Data Stream Processing on Modern Hardware, Constantin Pohl, Philipp Götze and Kai-Uwe Sattler (TU Ilmenau) (Slides)

  • (11.20 am - 11.40 am) Analyzing In-Memory Hash Join: Granularity Matters, Jian Fang (Delft), Jinho Lee (IBM Research), Peter Hofstee (IBM Research), and Jan Hidders (Vrije Universiteit Brussel) (Slides)

  • (11.40 am - 12 pm) Energy-Efficient Hash Join Implementations in Hardware-Accelerated MPSoCs, Sebastian Haas and Gerhard Fettweis (TU Dresden) (Slides)

Lunch Break (12.00-1.10 pm)

Session 3 (1.10 pm - 3.00 pm)

  • (1.10 pm -1.35 pm) Hardware-Accelerated Memory Operations on Large-Scale NUMA Systems, Markus Dreseler (HPI), Thomas Kissinger (TU Dresden), Timo Djürken (HPI), Eric Lübke (TU Dresden), Matthias Uflacker (HPI), Dirk Habich (TU Dresden), Hasso Plattner (HPI), and Wolfgang Lehner (TU Dresden) (Slides)

  • (1.35 pm - 2 pm) Adaptive Recovery for SCM-Enabled Databases, Ismail Oukid (TU Dresden), Anisoara Nica (SAP SE), Daniel Dos Santos Bossle (UFRGS), Wolfgang Lehner (TU Dresden), Peter Bumbulis (SAP SE), and Thomas Willhalm (Intel) (Slides)

  • (2 pm - 3 pm) "Alice in Wonderland, the Red Queen’s race, and microprocessor design in a world of Deep Learning", Tim Mattson, Senior Principal Engineer, Intel (Slides)

Coffee Break (3.00-3.30 pm)

Session 4 (3.30-5.00 pm)

  • (3.30 pm - 3.55 pm) SIAS-Chains: Snapshot Isolation Append Storage Chains, Robert Gottstein (TU Darmstadt), Ilia Petrov (Reutlingen University), Sergey Hardock (TU Darmstadt) and Alejandro Buchmann (TU Darmstadt) (Slides)

  • (4 pm - 5pm) "Anatomy of a Cloud-native Cognitive System", Aroop Pandya, Senior Technical Staff Member, IBM Watson


Workshop Co-Chairs

       For questions regarding the workshop please send email to

Program Committee

  • Nipun Agarwal, Oracle Labs
  • Christoph Dubach, University of Edinburgh
  • Nadathur Satish, Intel
  • David Schwalb, HPI
  • Sebastian Bress, DFKI
  • Shirish Tatikonda, Target
  • Christian Lang, Acelot
  • Vincent Kulandaisamy, IBM Analytics
  • Oded Shmueli, Technion
  • Spyros Blanas, Ohio State University
  • Stefan Manegold, CWI
  • Rene Mueller, IBM Research
  • Holger Pirk, MIT
  • Man Lung Yiu, Hongkong Polytechnic University
  • Mohammad Sadoghi, Purdue University

Important Dates

  • Paper Submission: Monday, June 12, 9 am EST (EXTENDED)
  • Notification of Acceptance: Monday, June 26, 2017
  • Camera-ready Submission: Friday, July 14, 2017
  • Workshop Date: Friday, September 1, 2017

Submission Instructions

Submission Site 

All submissions will be handled electronically via EasyChair.

Formatting Guidelines 

We will use the same document templates as the VLDB17 conference. You can find them here.

It is the authors' responsibility to ensure that their submissions adhere strictly to the VLDB format detailed here. In particular, it is not allowed to modify the format with the objective of squeezing in more material. Submissions that do not comply with the formatting detailed here will be rejected without review. 

The paper length for a full paper is limited upto 8 pages. However, shorter papers (4 pages) are encouraged as well.